IEEE Transactions on Electron Devices

Cynde Reid Gustafson wrote:
From: "Cynde Reid Gustafson" <nj@ccat.sas.upenn.edu>
Subject: IEEE Transactions on Electron Devices
Date: Sat, 19 Jan 2002 14:06:27 -0500

IEEE Transactions on Electron Devices

http://ieeexplore.ieee.org/lpdocs/epic03/RecentIssues.htm?punumber=16
(Link inactive 22 April 2005)

http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?puNumber=16
(Link active 22 April 2005)

- Growth of ultrahigh carbon-doped InGaAs and its application to
InP/InGaAs(C) HBTs
- Novel SOI p-channel MOSFETs with higher strain in Si channel using double
SiGe heterostructures
- Preparation of thin-film transistors with chemical bath deposited CdSe and
CdS thin films
- Microwave performance and modeling of InAs/AlSb/GaSAb resonant interband
tunneling diodes
- Two-dimensional quantum effects in nanoscale MOSFETs
- Breakdown voltage and reverse recovery characteristics of free-standing
GaN Schottky rectifiers
- Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs
MESFETs
- Formation of titanium silicide on narrow gates using laser thermal
processing
- Temperature behavior of visible and infrared electroluminescent devices
fabricated on erbium-doped GaN
- Clarification of floating-body effects on drive current and short channel
effect in deep sub-0 : 25 /spl mu/m partially depleted SOI MOSFETs
- Sub-100-nm vertical MOSFET with threshold voltage adjustment
- Arsenic/phosphorus LDD optimization by taking advantage of phosphorus
transient enhanced diffusion for high voltage input/output CMOS devices
- Accuracy of approximations in MOSFET charge models
- A method to extract mobility degradation and total series resistance of
fully-depleted SOI MOSFETs
- Sub-50-nm physical gate length CMOS technology and beyond using steep halo

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